1. Field of the Invention
The present invention relates to a decoding circuit where codes created by differential encoding are decoded.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a decoding circuit where codes created by differential logical conversion are decoded (hereinafter referred to as "sum decoding circuit") together with a differential logical circuit at the transmitting side of a communication system in the prior art. In FIG. 1, numeral 1 designates an input terminal where digital data a are input, numeral 2 designates a one-bit delay circuit constituted by one D-type flip-flop for example, numeral 3 designates an exclusive-OR circuit (hereinafter referred to as "EX-OR") for creating a difference, numeral 4 designates an output terminal where transmitting data b are output, numeral 5 designates a transmission path having noise, numeral 6 designates an input terminal where received data c including error are input, numeral 7 designates a one-bit delay circuit, numeral 8 designates an EX-OR for creating a sum, and numeral 9 designates an output terminal where data d after the sum decoding are output.
Next, operation will be described. The differential logical conversion at the transmitting side is expressed by the following formula. EQU b.sub.i =a.sub.i .sym.a.sub.i-1 ( 1)
Where a.sub.i designates data before the conversion, and b.sub.i designates data after the conversion, and a.sub.i and b.sub.i correspond to a, b respectively in FIG. 1. Subscript 1 represents the i-th data. Also .sym. represents the addition using 2 as modulus (modulo-2 addition). The input data a is input to one of two input terminals of the EX-OR 3, and also input to the one-bit delay circuit 2. Consequently, viewing the input data from a time series, the output signal of the one-bit delay circuit 2 is one-bit previous data a.sub.i-1. The EX-OR 3 performs modulo-2 addition of the data signal a, i.e., a.sub.i as one input and the output signal a.sub.i-1 of the one-bit delay circuit 2 as the other input, and obtains the output data signal b, i.e., b.sub.i. FIG. 2 shows the relation between a.sub.i and b.sub.i, for example.
The decoding on the receiving side is expressed by the following formula. EQU d.sub.i =c.sub.i .sym.d.sub.i-1 ( 2)
Where d.sub.i designates decoded data, and c.sub.i designates the received data before the decoding. Formula (2) represents that in order to obtain the i-th decoded data, one-bit previously decoded data [(i-1)th data] may be added to the i-th received data using 2 as modulus. So, the decoded data d is input to the one-bit delay circuit 7 and delayed by one bit, and then adding it to the received data c using 2 as modulus is performed in the EX-OR 8 thereby next decoded data d is obtained. This state is shown in c.sub.i, d.sub.i in FIG. 2.
In the sum conversion decoding at the receiving side, two problems occur as follows.
One is a problem in the initial value of the decoded data stream. Transforming the formula (2), it follows that EQU d.sub.i =c.sub.i .sym.c.sub.i-1 .sym.c.sub.i-2 .sym.. . . .sym.c.sub.2 .sym.c.sub.1 .sym.d.sub.o ( 3)
The decoded data d.sub.i is determined by the received data series c.sub.1 -c.sub.i and the initial value d.sub.o which cannot be determined only by the received data. The initial value d.sub.o is usually specified in the system whereby the problem is solved.
A second problem is in that since the data transmission path 5 includes noise, the received data c includes error, and after decoding this error propagates in the subsequent data through the sum conversion and so-called error propagation occurs. This state is shown in c.sub.i, d.sub.i of FIG. 2. In the received data c.sub.i, error occurs in c.sub.11 and c.sub.17. In the data d.sub.i after the decoding, not only does the error of c.sub.11 result in the error of one bit in d.sub.11, but the inversion of data continues subsequently and the error of the decoded data d.sub.i continues until the data is inverted again in the next received error bit c.sub.17 and returned to the original state. Thus, if a one-bit error occurs in the received data, all of the following decoded data is inverted and results in error until the next one-bit error of the received data occurs.
Since the sum decoding circuit in the prior art is constituted as described above, problems exist in that the error propagation is produced and the error is enlarged significantly in the decoding circuit.